Introduction to HDI Technology
High-density interconnect (HDI) printed circuit boards contain finer lines/spaces and higher connection densities than conventional PCBs. HDI technology enables:
- More routing channels for high I/O components
- Miniaturization of products
- High-speed signals with tightly matched lengths
- Improved electrical performance
With HDI PCBs, integrated circuits with over 2,000 I/O and 0.4mm pitch BGAs can assemble onto boards using stacked microvias and thin dielectric build-up layers.
Key drivers for utilizing HDI technology include mobile devices, wireless communications, automotive electronics, and medical systems seeking superior electrical performance within severely constrained volumes.
HDI Design Guidelines and Rules
To leverage the benefits of HDI, engineers must adopt new design methodologies. Some key HDI guidelines per IPC-2226A:
Layer Stacks and Materials
- Stackups with 3 to 12+ layers
- Thin core and prepreg dielectric
- Low-loss, tight-tolerance laminates
Line Width/Space
- Lines/clearances under 8 mil (0.20mm)
- Spaces as fine as 2 mil (0.05mm)
Via Structures
- Microvias with under 8 mil diameters
- Stacking/tiering microvias for routing
Copper Weights
- Core metal over 2 oz (70 μm) thickness
- Build-up layers 0.5-1 oz (15-35 μm) metal
HDI Build-Up Layer Technology
HDI PCBs utilize additional thin circuit layers bonded onto cores using dielectric laminates. This allows trace geometries finer than conventional methods permit.
Dielectric Build-Up Layers
Thin insulating prepreg or film adhesives clad with copper foil. Common materials:
- Polyimide
- FR-4 composites
- Iso-material blends
- Liquid polymer coatings
These laminates coat over cores with build-up metal layers on either side of boards. Dielectrics possess tight thickness tolerances.
Pattern Plating Process
A semi-additive process selectively deposits and etches copper circuits onto laminate layers, which plates then get etched to isolate individual traces.
High density lines/spaces result from precision lithography to define plating areas combined with thin resist and copper. The additive plating avoids etched undercuts.
Microvia Interconnections
Small vias generated by laser drilling connect outer build-up layers through interposers to inner structure layers underneath, either pads or capture vias. The microvias occupy less space versus through-hole vias while permitting layer-to-layer connections.
Laser via diameters scale below 8 mils thanks to precise beam accuracy. Plating then fills holes to form barrel interconnects.
Core Layer and Final Metal Considerations
In addition to build-up technology, factors like core layer designs and outer surfaces influence HDI performance.
Core Dielectric Layers
Low-loss, tight-tolerance prepreg core materials maintain signal quality under high speeds, frequencies and layer counts:
- Thermoset resins (FR-4, BT Epoxy)
- Thermoplastics (LPC, PTFE composites)
- Ceramics (Alumina, Aluminum Nitride)
Final Surfaces
Final metal layers deposited on the outside of an HDI PCB serve vital electrical and assembly functions:
Outer Signal Layers: Accommodate fine delay matching lines.
Solder Masks: Help define solderable areas. Low coefficient of thermal expansion (CTE).
Surface Finishes: Protect pads while enabling solderability. Examples: ENIG, Immersion Silver, OSP.
Legend Ink: Identify components. Resistance to cleaning processes.
HDI Manufacturing Process Overview
Fabricating HDI boards with thin dielectrics, high layer counts and fine geometries involves specialized sequential building steps:
1. Core Lamination
Start with an insulating dielectric layer clad with copper foils bonded onto both sides that will form a robust inner foundation.
2. Drilling and Plating
Mechanically drill holes for through vias in the core then electroplate conductive barrel surfaces.
3. Outer Layer Imaging
Photoinage and etch CU circuits on either side of the core layers.
4. Build-Up Layer Bonding
Adhere sequential dielectric film/prepreg layers. Repeat to build HDI layer count. Laser drill microvias.
5. Build-Up Metalization
Semi-additively plate and define traces on build-up layers. Repeat to form multilayer interconnects.
6. Final Surfaces
Deposit solder mask, legend, and metal finish onto the HDI stackup.
7. Route and Test
Electrically test circuits then depanelize individual boards.
The combination of thin, sequential laying with laser drilling and precision imaging enables HDI PCBs containing dense interconnects with fine features.
Below outlines a few key advantages and limitations when working with HDI technology during PCB design and fabrication:
| Advantages | Limitations |
|---|---|
| Enables miniaturization of electronics | More fabrication process steps |
| Finer lines and spaces increase routing channels | Tight tolerance materials controls |
| Microvias provide high I/O density | Narrow process margins for thin layers |
| Layer counts over 20 possible | High development costs |
Conclusion
In summary, high-density interconnect PCB technology facilitates complex multilayer boards with stacked microvias and fine line geometries not achievable with conventional manufacture approaches. This permits far greater interconnect densities and electrical performance needed in compact, cutting-edge electronic devices and assemblies. However, the powerful HDI techniques also introduce tighter design rules, material requirements and fabrication sequences to manage versus standard PCBs.
Frequently Asked Questions
What are the main benefits of HDI PCB technology?
The principle benefits of HDI are increased routing channels through additional thin circuit layers, smaller via structures enabling higher I/O component densities, and the ability to tightly match electrical lengths across layers to maximize high-speed signal integrity.
What are some key HDI design considerations?
When leveraging HDI technology, designers must follow tighter constraints and rules regarding line/space dimensions, layer dielectrics, microvia implementation, and lamination sequences. Adhering to HDI design guidelines ensures manufacturability and interoperability.
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