Mastering SPICE Simulation in Altium Designer

 

Introduction

SPICE (Simulation Program with Integrated Circuit Emphasis) is a powerful analog circuit simulation tool for predicting circuit behavior. Performing SPICE simulations in Altium Designer allows verifying circuit performance early in the design flow. This prevents finding issues late in prototype testing.

However, running accurate and efficient SPICE simulations requires understanding simulator capabilities, simulation models, analysis types, and simulation settings. Mastering these factors helps designers reliably optimize circuits pre-manufacture.

This guide covers SPICE simulation best practices for Altium Designer.

Altium Designer SPICE Simulation Overview

Altium Designer integrates the following SPICE platforms:

• LTspice - Provided by Analog Devices, LTspice is robust SPICE environment tailored for switch-mode and analog circuits.
• Ngspice - Open-source SPICE platform with all standard analyses and model libraries.
• SmartSpice - Developed by Sigrity, SmartSpice specialized simulations include power integrity, thermal, and EMI.

Key features include:

• Direct import of Altium schematics into simulator
• Extensive component model libraries
• Customizable analysis and simulation settings
• Waveform visualization of results
• Comparison of multiple simulations

This built-in SPICE integration avoids exporting netlists and using external tools. Designers can seamlessly co-simulate circuits alongside board layout.

Typical SPICE Analyses

Common analyses performed in Altium Designer's SPICE environment include:

DC Sweep - Sweeps a DC voltage or current source across a range to determine operating point voltages and currents. Plots output variables versus input sweep.

AC Sweep - Sweeps AC input signal frequency to characterize frequency response. Determines gain, phase, and impedance versus frequency.

Transient - Analyzes output waveform response over time to a time-varying input stimulus. Determines rise time, fall time, settling time, overshoot, etc.

Noise - Calculates overall noise using device noise models. Estimates signal-to-noise ratio.

Temperature - Simulates circuit performance over a range of ambient temperatures using thermal models. Determines temperature coefficients.

Monte Carlo - Performs multiple simulation runs with component value variations based on tolerances to determine resulting performance distribution.

Configuring Simulation Parameters

The simulation parameters control the type of analysis performed and how it is run:

Analysis Type - Choose required analysis e.g. DC Sweep, AC Sweep, Transient.

Inputs - Add stimulus sources such as voltage, current, voltage sweep.

Duration - Set analysis duration for transient simulations.

Time steps - Specify timestep size for transient analysis. Smaller steps improve accuracy.

Temperature - Set ambient temperature if thermal analysis is enabled.

Tolerances - Enter component tolerance values for Monte Carlo analysis.

Outputs - Select output voltage or current nodes to plot results.

Correctly configuring these parameters ensures the simulation provides the required performance data.

Adding Simulation-Based Models

For accurate simulations, select models matching the real-world devices:

Passive models - Resistors, capacitors, inductors use RLC models. Specify values and parasitics.

Semiconductor models - Diodes, BJTs, MOSFETs use SPICE models from manufacturers. Check model matches datasheet.

Integrated circuit models - Op amps, regulators, ICs use SPICE macro models from datasheet. Verify pin order.

Board models - Transmission lines, planes can be modeled for signal integrity analysis.

Thermal models - For temperature analysis, add thermal resistance models (Rth) and capacitance (Cth).

Using vendor-provided SPICE models produces far superior correlation to measured results rather than generic models.

Adding Simulation-Based Effects

Besides basic components, simulations can include real-world effects:

Parasitics - Add parasitic resistances, inductances, and capacitances to improve modeling accuracy.

Temperature - Specify temperature ranges and device temperature coefficients.

Noise - Enable noise simulation using material and device noise models.

Process variation - Apply statistically distributed component value variation for Monte Carlo analysis.

Fault injection - Introduce open, short, or impedance faults at chosen locations to simulate defects.

Incorporating these enhances simulation fidelity to the actual fabricated circuit behavior.

Recommended Simulation Practices

Follow these guidelines to run effective SPICE simulations:

• Start with default simulation settings and generic component models initially.
• Make incremental adjustments to parameters, one change at a time, to understand effects.
• Validate simulations against known results from datasheets or textbooks.
• Add increasing model detail in stages: nominal values, parasitics, vendor models, temperature, etc.
• Clearly name and document all simulations for future reference.
• Correlate simulation results back to calculations and theory to ensure accuracy.
• Segregate design simulations from fault injection “what-if” simulations.

Adhering to disciplined, incremental simulation practices prevents misinterpretation and verifies predicted performance.

Simulating Complex Systems

For simulating large systems, use these techniques:

Simplify - Replace complex subcircuits with behavioral models. Remove unneeded details.

Partition - Divide into smaller circuits to simulate individually, then reintegrate.

Abstract - Model external systems by their key parameters and inputs/outputs.

Approximate - Linearize about operating points to simplify equations.

Script - Write scripts to automate simulation of multiple scenarios.

Strategically reducing simulation complexity enables practical analysis without excessive compute time or memory.

Common SPICE Simulator Issues

Watch out for these common issues using SPICE:

Convergence failure - Poor configuration causes iterative solver to fail. Simplify or adjust tolerance, time steps.

Unrealistic results - Incorrect models or values produce impossible results. Double check all entries.

Long simulation times - Complex simulations can take hours or get stuck. Simplify circuits or partition.

Truncated waveforms - Transient too short misses important dynamics. Extend duration.

Stability issues - Feedback circuits may have oscillation or ringing if Q not properly damped.

Noise obscures signal - Excessive or overwhelming noise. Adjust noise simulation settings or filter.

Careful simulation setup, model selection, and result vetting avoids these reliability and accuracy pitfalls.

Integrating Simulation into Design Flow

Combine simulation tightly within the overall IC/PCB design process:

Schematic capture - Enter candidate circuit with initial component values.

Simulation - Simulate circuit with nominal values. Assess performance versus requirements.

Design improvement - Refine circuit topology and values based on simulation.

Model detail - Add parasitics, vendor models, non-ideal effects for realistic simulation.

Monte Carlo analysis - Simulate statistical performance distribution considering tolerances.

Verification - Correlate simulated performance with hand calculations and theory.

This design-simulate-refine loop uncovers issues early, before committing to physical implementation.

Simulating Prior to PCB Layout

For PCBs, simulate circuits before layout:

• Confirms schematic circuit meets system requirements before layout effort.
• Checks noise, stability, and sensitivity to component tolerances.
• Validates key parameters versus hand calculations.
• Highlights components needing tight tolerances or layout matching.
• Indicates performance most sensitive to parasitics to guide layout considerations.
• Estimates tempco effects and operating temperature range.
• Provides benchmark to compare against post-layout simulations.

Performing pre-layout simulation reduces late-stage redesign risk after detailed layout.

Simulating After PCB Layout

Follow layout with post-layout simulation:

• Incorporates PCB layout parasitics: line lengths, coupling, shapes, etc.
• Adds plane impedances and transmission line effects.
• Confirms performance requirements still met considering layout impact.
• Validates power integrity including supply noise, throttling, and decoupling.
• Checks susceptibility to layout-induced noise coupling.
• Assesses signal integrity like rise/fall times, impedance discontinuities, etc.

Post-layout simulations verify the PCB implementation achieves the intended simulated performance.

Simulation Data Exchange

Seamlessly exchange simulation data between tools:

Netlist export - Export netlist from PCB layout into simulator tool.

Parasitic inclusion - Import parasitic data from PCB layout tool after extraction.

Model libraries - Share simulation models between schematic, layout, and simulator tools.

Waveform exporting - Export simulated waveforms for cross-probing in other tools.

Settings transfer - Transfer key settings like tolerances between schematic and simulator tools.

Automating simulation data exchange with PCB tools enables efficient design validation workflows.

Simulator Tool Integration

Integrate external simulator tools where advantageous:

• Co-simulate analog, digital, electromagnetic portions in dedicated solvers.
• Utilize proprietary simulation algorithms unavailable in default simulators.
• Leverage GPU acceleration and distributed processing for large simulations.
• Access advanced modeling languages like Verilog-A or VHDL-AMS.
• Employ exotic analysis types like multitone distortion or phase noise.

Interoperating with leading-edge simulation engines expands analysis capabilities.

Simulator Tool Interoperability

Maintain interoperability when using multiple simulators:

• Standardize on common netlist formats like SPICE, CDL, Verilog.
• Keep central component model libraries compatible across tools.
• Script automated model conversions into tool-specific formats.
• Use tool-agnostic APIs like C, Python to coordinate tool integration.
• Run correlation benchmarks using reference circuits between tools.

Simulator interoperability enables flexible swapping of the right engine for each simulation task.

Deploying Simulations

Properly manage simulation content:

Revision control - Check simulation netlists, configurations, and results into source control system.

Documentation - Record simulation objectives, assumptions, known issues to inform design decisions.

Tool integration - Provide quick access to simulations from within design tools for cross-probing.

Automation - Script routine simulations for regression testing and what-if scenarios.

Simulation reviews - Review simulation process and results as part of design reviews to identify improvements.

Well-maintained, tool-integrated simulations become valuable organizational assets and prevent knowledge loss.

Simulating Fault Conditions

Beyond nominal operation, simulate electrical faults:

• Short circuits - simulate low-impedance connections between nets.
• Open circuits - add high impedance between nets to simulate broken tracks.
• Parasitic impedance - represent degraded connections with added resistance, capacitance, or inductance.
• Supply faults - vary supply voltage, noise, and ripple to force brownout conditions.
• Timing faults - inject signal timing errors like spurious edges or delays.
• Part swap - substitute models to assess replacement component compatibility.

Fault simulations validate fault tolerance, safety mechanisms, and redundancy provisions.

Simulating Manufacturing Defects

Model potential manufacturing defects:

• Missing parts - omit components to detect any single-point failures.
• Wrong values - substitute with out-of-spec values.
• Solder bridges - connect unrelated nets with low impedance.
• Open vias - insert high impedance in series with via stacks.
• Skewed impedance - add distributed impedance representing unmatched trace widths or shapes.
• Warped boards - tweaking geometry can check performance sensitivity.
• Contamination - add parasitics representing ionic, adhesive, or particulate contamination.

Worst-case defect modeling provides early verification of manufacturing quality controls and process margins.

Simulating Aged Components

Model effects of component aging:

• Increase/decrease values based on datsheet aging data.
• Add higher/lower impedance resistances due to corrosion.
• Reduce turn-on time, increase leakage of transistors/diodes over lifetime.
• Add hysteresis and nonlinearities for aged inductors.
• Increase ESR, leakage, dissipation factor for aged capacitors.
• Reduce beta, increase Vf for older bipolar transistors and diodes.
• Add noise representing aged components.

Aged component simulations help predict system MTBF and guide design refresh requirements.

Correlating Lab Measurements

Validate simulations against empirical data:

• Measure performance of breadboard or prototype.
• Compare waveforms and key metrics between simulation and measurement.
• If differences, iteratively refine simulation based on feedback from lab.
• Add missing non-ideal effects: noise, parasitics, temperature, package behaviors.
• Double check models against datasheets if discrepancies.
• Consider test setup limitations causing measurement artifacts.
• Quantify simulation accuracy versus measurement for reporting.

Careful correlation provides a calibrated simulation methodology for future designs.

Simulating Extreme Conditions

Test performance limits through extreme simulations:

• Temperature extremes - simulate minimum and maximum operating temps.
• Voltage extremes - run simulations at minimum and maximum supply voltages.
• Max load conditions - simulate highest possible capacitive, resistive, and inductive loading.
• Max clock frequencies - test performance at system speed limits.
• Combinations - combine above stressors to mimic worst-case realistic conditions.
• Beyond rated conditions - push beyond specs to test guard band.

Simulation under extreme conditions identifies design margin and risks before manufacturing.

Simulating Design Optimizations

Use simulations to optimize the design:

• Change values - try different nominal values to meet requirements.
• Swap components - check substituting equivalent parts.
• Add/remove parts - simulate adding filtering or removing unused components.
• Topology changes - try alternative subcircuit configurations.
• Structure options - change layout-dependent structures like transmission lines or planes.
• Review trade-offs - evaluate costs/benefits of high-performance components.
• Assess options - quantitatively compare design alternatives.
• Automate - script parametric simulations sweeping design variables.

Simulation enables rapid optimization iterations without costly prototyping.

Setting Tolerances Based on Monte Carlo Analysis

Leverage Monte Carlo analysis to determine suitable component tolerances:

• Start with standard tolerance values (1%, 5%, 10%, etc.).
• Perform Monte Carlo simulations with 100+ random samples.
• Assess resulting distribution of system performance metrics.
• Determine percentage of samples meeting requirements.
• Relax tolerances on non-critical components incrementally until yields meet target.
• Tighten tolerances on critical components driving performance spread.

This balances tolerances and system cost based on simulated yield requirements.

Reusing Simulations

Make simulations reusable:

• Modularize circuits into subcircuits to re-use in future designs.
• Build libraries of common simulation models and configurations.
• Categorize simulations by design type for easy searching.
• Generalize simulation scripts using variables for broad applicability.
• Document assumptions, methods, and usage clearly in simulation.
• Keep simulations under configuration management like other design artifacts.

Re-using validated simulation modules and best practices slashes maintenance effort while ensuring high fidelity.

Training and Mentoring

Cultivate simulation expertise across teams:

• Conduct formal SPICE simulation training covering best practices.
• Hold seminars on advanced simulation methods.
• Mentor junior engineers through hands-on circuit simulations.
• Encourage dialog between design and simulation teams to improve processes.
• Foster internal consulting group to assist projects with simulation.
• Enable engineers to cross-train between design and simulation roles.

Developing multi-disciplinary simulation skills fortifies tribal knowledge and succession planning.

FAQs

What is the advantage of SPICE over algebraic circuit solvers?

SPICE handles complex nonlinear circuits unsolvable through algebraic methods. It also models non-ideal component behavior lacking in algebraic solvers.

When should parasitic elements be added into a simulation?

Introduce parasitics incrementally after achieving circuit functionality with ideal models first. Prioritize parasitics known to significantly impact performance.

How can I reduce computation time for large circuit simulations?

Simplify less critical subcircuits. Limit precision of non-critical output results. Partition into separate netlists. Utilize multi-core and distributed processing.

What is the best practice for validating a simulation?

Double check simulation parameters match the intended configuration. Review outputs against hand calculations and theory for the given inputs. Perform correlation to lab measurements.

How can I check if my simulation convergence is adequate?

Check convergence errors are small relative to result magnitudes. Increase iterations and relax tolerances until results stabilize. Compare multiple time step sizes.