Ever wonder what separates modern multi-gigabit circuit boards from simpler, slower legacy boards? As data rates accelerate with new standards like USB 3 and HDMI 2.1, accounting for physical signal integrity principles becomes critical.
High speed design practices optimize PCB layouts to limit signal degradation across traces, interfaces, and components. Applying these methodologies prevents errors, lost data, and compatibility issues in high frequency systems transmitting beyond ~250 MHz.
This guide serves as your introduction to high speed PCB design. Follow along as we cover topics like:
- Defining high speed signals
- Understanding signal integrity
- Modeling transmission lines
- Planning layer stacks
- Routing techniques
- Simulations and testing
Let’s get started appreciating the importance of modern high speed design!
What Qualifies as a High Speed Signal?
Simply put, high speed signals see edge rates faster than the propagation delay across a printed circuit board trace in a given dielectric material. This results in transmission line effects that distort waveform quality.
But what rate meets this threshold? While no fixed cutoff exists, we can make some generalizations.
Rule of Thumb Frequencies
As a starting point, signals above ~250 MHz or transitioning faster than 1-2 ns tend to require high speed treatment. However, even multi-megahertz signals can behave as higher speed “fast logic” depending on physical lengths.
In particular cases, lower frequencies down into the tens of megahertz may need attention when traces span many inches crossing a board. Conversely, short traces under an inch on server blades can tolerate well over 300 MHz before transmission line techniques become critical.
Identifying Symptoms of High Speed Issues
Practically speaking, unexplained glitches emerge above ~100-200 MHz which suggest SI issues. If communication reliability drops sharply between generations of products or interconnect distances change, suspect high speed links.
You may witness issues like:
- Data corruption requiring retransmission of packets
- Jitter causing bit errors from poor signal quality
- Rise/fall time skew degrading eye patterns and noise margins
Investigate any unexplained physical layer flakiness when transitioning to faster rates as a cue to learn high speed design practices. Their need is apparent to implement robust multi-gigabit links.
Now that you can identify scenarios requiring a high speed approach, let’s explore why signal integrity matters.
Signal Integrity Induces High Speed Constraints
Simply routing traces arbitrarily like low speed digital controls will not cut it for today’s serial buses hitting 6 Gbps and above. At high frequencies, conductors exhibit transmission line behaviors producing reflections and losses.
We must carefully control trace impedances, match lengths, meet timing rules, mitigate cross-talk, and more. This discipline is signal integrity engineering – maintaining sufficient waveform fidelity such that the receiver can correctly reconstruct the digital 1’s and 0’s.
Let's visually see how traces can corrupt signals at high speeds using simulations.
Reflections From Impedance Mismatches
When a fast edge hits a section of PCB trace with different impedance, voltage reflections occur. See how 30 Ω trace impedance causes over/under-shoot on this pseudo-random bit sequence:
The discontinuity degrades rise/fall symmetry and timing. Without remedial actions, too much impedance mismatch causes eye closure.
Inter Symbol Interference
When fast rise times approach same length delays as symbol periods, previously transmitted signals can interfere with incoming bits. This inter-symbol interference (ISI) leads to incorrect sampling:
Stubs, vias, components, and poor termination foster ISI by reflecting or delaying parts of fast wavefronts. ISI must be mitigated through layout.
You can now appreciate why high frequency systems require specialized modeling and routing knowledge for clean signal transport acceptable to destination devices. Next let's introduce transmission line theory which is the basis of signal integrity practices.
Modeling Traces as Transmission Lines
To master high speed design, we must discard simplistic notions of traces behaving as plain conductors. Interconnects above a few inches especially act as transmission lines - guiding electromagnetic waves like coaxial cables or antenna feed lines do.
For proper impedance targeting and termination, modeling trace parameters as transmission lines applies. Let’s breakdown key transmission line concepts and definitions you will encounter using a microstrip trace cross-section:
Where:
- H – Dielectric thickness
- W – Trace width
- T – Trace thickness
- εr – Dielectric constant
- Zo – Characteristic Impedance
This generalized model handles voltages, currents, distances and time delays through mathematical expressions. Combined with frequency domain analysis, we can predict losses and reflections.
Characteristic Impedance
The intrinsic, designated impedance of a transmission line when endless with no discontinuities. Controlled by physical dimensions, materials, and nearby dielectrics. Serves as reference for termination resistor values.
Propagation Constant (γ)
Defines amplitude loss and phase change per unit length during wave propagation. Key components:
Attenuation Constant (α) - Rate of signal decrease from conductor and dielectric losses
Phase Constant (β) – Phase shift rate from transit delay
Together they characterize velocity, travel time, and arrival amplitude.
Reflection Coefficient
Quantifies the impedance mismatch at a load discontinuity generating reflected voltage waves back toward the source. Defined as:
Γ = (ZL − Z0) / (ZL + Z0)
Where ZL is load impedance and Z0 is line impedance. Perfect match equals 0, while complete mismatch approaches 1.
Identifying where reflections stem from by correlating physical length, velocity factor, and return loss plots allows mitigating excessive discontinuities.
This briefly summarizes widely used transmission line concepts useful for signal integrity analysis as traces electrically lengthen with frequency. If new to you, don’t worry - we will link helpful resources to dive deeper into characteristic impedances and other parameters later.
Armed with the right transmission line knowledge, you are equipped to implement modeling procedures and constraints necessary for routing high speed signals across a PCB. Time to explore practical board layout techniques.
High Speed Routing Techniques
With design principles established, now we tackle the details - planning layer stacks, matching lengths, managing vias, eliminating stubs, and more. Careful high-speed layout avoids signal corruption ensuring the receiver sees a clean waveform.
Let’s survey essential best practices for error-free high speed routing and mitigating common causes of signal degradation.
Layer Stackup Planning
First critical decision - planning differential pair routing layers and plane arrangement surrounding them. Common goals:
Isolation - Maximize isolation from noisy digital pairs
Symmetry - Ensure similar dielectric constants above and below routed signals. Avoid directly adjacent asymmetric planes spanning ground and power.
Shielding - Helpful to sandwich between constant potential planes for crosstalk protection.
Dedicated Layers - Place key pairs on their own internal layers without other signals jumping layers to cross.
Differential Stubs – Ensure reference/ground planes under pairs span beyond routed signals minimizing return path discontinuities.
Get layer planning right from the start and signals route cleanly.
Impedance Control
With stackup set, dial-in target differential impedance (typically 90-110 Ω). Solve dimensions with calculators or simulate prior to routing length matching:
Tune trace width/spacing and refer to impedance tables if dimensions shift in layout.
Managing Vias
Limit vias which cause discontinuities. But when needed:
Tent – Surround entire pad with ground shape stitched to plane. Reduces stub.
Back drill – Drill out unused portion of via barrel below pad after plating.
Mitigating Cross-Talk
Use ground floods, spacing, and avoid 90° crosses:
Symmetrical Branching
Balance trace lengths through symmetrical equidistant branching:
There are many additional guidelines, but this covers the major areas to focus on.
For complete details and dimensional examples tailored to data rates and media, refer to an IPC-2152 high speed design guide. If new to high speed, don’t route blindly - educate yourself further!
That covers the PCB physical layout stage critical for signal integrity. Next we must validate designs through accurate modeling.
Simulation and Verification
To confidently certify a high speed design before manufacturing, simulate actual constructed layer stacks and traces with 3D field solvers. This reveals potential issues
